Semiconductor based integrated circuits (ICs) are complex and contain millions of circuit devices such as transistors and millions of interconnections between the circuit devices. Designing, testing, and verifying the functionality of complex circuits cannot be accomplished manually, and designers use computer based electronic design automation (EDA) tools for creating schematics, layouts, simulation, and verification of the complex ICs such as radio frequency (RF) circuits.
Conventionally, during the designing and testing phases of RF circuits, designers create schematic designs of RF circuits prior to creating corresponding layouts (also referred to as layout designs) of the RF circuits. When a schematic designer first creates a schematic design of an RF circuit, the schematic designer may use parameters determined by simulating the RF circuit without knowing the constraints for a corresponding layout design. For example, the schematic designer may not know if a corresponding layout design for the schematic design can even be generated. While the schematic design includes logical components and logical connections within the RF circuit, the corresponding layout design includes physical components and physical connections. The layout design therefore may have placement and/or routing constraints. For example, in a layout design, a layout designer has to consider whether floor space is available for a component or routing a connection and whether a connection can be routed in a straight line.
The conventional methods of designing and testing RF circuits may therefore include multiple and cumbersome iterations. A schematic designer generates a schematic design without the knowledge of physical constraints in a layout design. When a layout designer generates a layout design corresponding to the schematic design, the layout designer has to provide feedback to the schematic designer to generate a new schematic design accounting for the physical constraints. The new schematic design may again not be within the physical constraints or may generate other unforeseen physical design problems. Furthermore, based on the physical constraints, the schematic designer may have to modify impedance requirements. Therefore, it may take multiple iterations and a significant amount of time to achieve a schematic design and a corresponding layout design that are in sync with each other.
For example, a schematic designer may generate a straight transmission line between a point A and a point B in an RF circuit. A layout designer may encounter various blocks in the path of the straight transmission line. The layout designer may therefore have to change the configuration of the transmission line layout, e.g., introduce bends, to route around the blocks. The layout designer may then have to communicate the change in configuration to the schematic designer. The schematic designer may modify the transmission line in the schematic design to accommodate the change the layout configuration. In other words, the changes in the layout design of the transmission line may have to be communicated back multiple times to the schematic design of the transmission line.